Ads
    Related paper
  1. Review Paper on Area Efficient Vedic Multiplier using Barrel Shifter
  2. Review Paper on Area Efficient Vedic Multiplier using Barrel Shifter
  3. A Novel High Speed and Area Efficient Vedic Multiplier Designing using Carry Select Adder
  4. EFFICIENT FPGA BASED MATRIX MULTIPLICATION USING MUX AND VEDIC MULTIPLIER
  5. IMPLEMENTATION OF OPTIMIZED MULTIPLIER-ACCUMULATOR (MAC) UNIT WITH VEDIC MULTIPLIER AND FULL PIPELINED ACCUMULATOR: A REVIEW
  6. VLSI Design of Low Power Reversible 8-bit Barrel Shifter
  7. LOW POWER BARREL SHIFTER DESIGN USING COMPLEMENTARY AND PSEUDO NMOS LOGIC
  8. Review on Floating Point Multiplier Using Vedic Mathematics
  9. Design and Implementation of Ternary Bidirectional Barrel Shifter Using Multi-Valued Reversible Logic
  10. Review on FPGA Implementation of 16*16 Vedic Multiplier in VHDL Environment