Ads
    Related paper
  1. A Design Of A Low Power Delay Buffer Using Ring Counter Addressing Schemes
  2. Interconnect Delay and Power Optimization Using Schmitt Trigger as Alternate Approach to Buffer Insertion
  3. POWER AND AREA EFFICIENT DESIGN OF COUNTER FOR LOW POWER VLSI SYSTEM
  4. Design of CMOS Tapered Buffer for High Speed and Low Power Applications using 65nm Technology
  5. Low Power-Delay Design of 4-Bit ALU Using GDI Technique and Its Comparison
  6. An Efficient Design for Reduction of Power Dissipation in Johnson Counter using Clock Gating
  7. Design of Low Power Voltage Controlled Ring Oscillator Using MTCMOS Technique
  8. DESIGN OF LOW POWER AND DELAY SRAM MEMORY FOR SMART VEHICLES
  9. POWER-DELAY EFFICIENT ASYNCHRONOUS DESIGN APPROACH USING GALEOR
  10. Design and Analysis of Dynamic Comparator with Reduced Power and Delay