Ads
-
Related paper
- Leakage Power Minimization in ST-SRAM Cell Using Adaptive Reverse Body Bias Technique
- PERFORMANCE OF LEAKAGE POWER MINIMIZATION TECHNIQUE FOR CMOS VLSI TECHNOLOGY
- Minimization of Leakage Current of 6T SRAM using Optimal Technology
- Design of Low Power 10T SRAM Cell with MTCMOS Technique
- Analysis of Design of Schmitt Trigger Based SRAM Cell Using a Novel Power Reduction Technique
- LEAKAGE POWER REDUCTION IN DEEP SUB MICRON SRAM DESIGN - A REVIEW
- Comparison of Conventional 6T SRAM cell and FinFET based 6T SRAM Cell Parameters at 45nm Technology
- Low Power 1 bit Adiabatic SRAM Cell Design
- Novel Design of Low Power Nonvolatile 10T1R SRAM Cell
- Asymmetric SRAM Memory Cell for Power Reduction